The present invention generally relates to an integrated circuit for concurrent flash memory and more particularly, to an integrated circuit for concurrent flash memory having an uneven array architecture which provides improved flexibility relative to prior circuits.
Semiconductor memory devices, such as flash memory devices, typically employ integrated circuits having arrays of memory cells to store and access electronic data. One type of integrated circuit, commonly referred to as a concurrent flash memory circuit, utilizes multiple arrays of memory cells to allow reading and programming/erasing functions to be performed simultaneously. Particularly, in this type of circuit, a first bank of memory cells comprising one or more arrays can be read while a second bank of memory cells comprising different arrays is concomitantly programmed or erased.
One example of a prior concurrent flash memory circuit is illustrated in FIG. 1. Circuit 10 includes four memory cell arrays 12, 14, 16, and 18 of equal size (e.g., 1X). Each array 12-18 includes a plurality of non-volatile memory cells (not shown) which are connected together in a two-dimensional configuration of rows and columns. Circuit 10 further includes four X-decoder blocks 20, 22, 24, and 26 which are respectively and communicatively coupled to arrays 12, 14, 16 and 18, and four Y-decoder blocks 28, 30, 32, and 34 which are respectively and communicatively coupled to arrays 12, 14, 16 and 18. Each X-decoder block 20-26 is coupled to address buses 36, 38 through logic circuitry 44, 46, respectively, and includes a plurality of conventional X-decoders which are effective to select certain rows of the memory arrays 12-18, based upon signals received from address buses 36, 38. Each Y-decoder block 28-34 is coupled to address buses 36, 38 through logic circuitry 44, 46, respectively, and includes a plurality of conventional Y-decoders which are effective to select certain columns of the memory arrays 12-18, based upon signals received from address buses 36, 38.
Circuit 10 further includes four sense amplifier blocks 48, 50, 52 and 54 which are communicatively coupled to arrays 12, 14, 16 and 18, respectively. Sense amplifier blocks 48, 50, 52 and 54 are coupled to data buses 40, 42 through logic circuitry 56, 58, respectively, and include a plurality of sense amplifiers that facilitate the reading and programming/erasing of data from and into arrays 12-18. Circuit 10 further includes a register 60 which determines which arrays 12-18 will be cooperatively linked to form each memory bank (i.e., to form memory banks 1 and 2). In alternate embodiments, concurrent memory operation may be facilitated by use of a metal option layer.
Address bus 36 and data bus 40 may be used to access a first bank of arrays (i.e., bank 1), which may include one or more cooperatively linked arrays 12-18, and address bus 38 and data bus 42 may be used to access a second bank of arrays (i.e., bank 2), which includes the remaining arrays. In this manner, circuit 10 allows a first memory operation, such as reading, to be performed on the first bank of arrays (i.e., bank 1), while a second memory operation, such as programming or erasing, is simultaneously performed on the second bank of arrays (i.e., bank 2).
While prior concurrent flash memory circuits, such as circuit 10, are effective to simultaneously perform reading and programming/erasing functions, they have limited flexibility. Particularly, the number of available bank size combinations (i.e., the available size combinations for the first bank and the second bank) is dependent upon the size of the various arrays which selectively form the memory banks.
Because the sizes of the arrays are identical in a conventional concurrent flash memory circuit, the number of possible bank size combinations for concurrent read and program/erase operation is limited. By way of example and without limitation, a conventional concurrent flash memory device including four arrays each having a size of 1X can provide only three unique bank size combinations for concurrent read and program/erase operation. That is, the possible size combinations for the first bank (e.g., the read bank) and the second bank (e.g., the program/erase bank) are limited to 1X/3X (e.g., one array for reading and three arrays for programming/erasing), 2X/2X (e.g., two arrays for reading and two arrays for programming/erasing), and 3X/1X (e.g., three arrays for reading and one array for programming/erasing).
Some prior flash circuits have attempted to implement three arrays in an uneven architecture. Such an architecture is discussed in L. G. Fasoli et al., A 64Mb User-Configurable Dual Bank Burst Mode FLASH memory, Digest of the Non-Volatile Semiconductor Memory Workshop Aug. 12th-16th, 2001, at p. 33. The above-referenced architecture implements three arrays in a 1X, 1X, 2X uneven configuration. While this architecture is user-configurable, it provides no additional bank size combinations than prior 1X, 1X, 1X, 1X configurations. That is, the possible size combinations for the first bank (e.g., the read bank) and the second bank (e.g., the program/erase bank) are limited to 1X/3X (e.g., one array for reading and two arrays for programming/erasing), 2X/2X (e.g., two arrays for reading and one array for programming/erasing), and 3X/1X (e.g., two arrays for reading and one array for programming/erasing).
There is therefore a need for a new and improved integrated circuit for concurrent flash memory having an uneven array architecture which provides improved flexibility and additional bank size combinations.
A first non-limiting advantage of the invention is that it provides an integrated circuit for concurrent flash memory having improved flexibility.
A second non-limiting advantage of the invention is that it provides an integrated circuit for concurrent flash memory having an uneven array architecture which provides for many different bank size combinations for concurrent read and program/erase operation.
According to a first aspect of the present invention, an integrated memory circuit is provided. The integrated memory circuit includes a first array having a first amount of non-volatile memory cells; a second array having a second amount of non-volatile memory cells; a third array having a third amount of non-volatile memory cells; and a fourth array having a fourth amount of non-volatile memory cells; wherein the third amount is different from the first amount. The first, second, third and fourth arrays are cooperatively linked in a manner which allows a first bank of memory cells including at least one of the first, second, third and fourth arrays to be read, while a second bank of memory cells including the remaining of the first, second, third and fourth arrays is simultaneously programmed or erased.
According to a second aspect of the present invention, an integrated circuit for concurrent flash memory is provided. The integrated circuit includes a first array of flash memory cells; a second array of flash memory cells; a third array of flash memory cells; and a fourth array of flash memory cells; wherein the first and second arrays are of a first size and the third and fourth arrays are of a second size different from the first size. The first, second, third and fourth arrays are coupled together in a manner which allows a first bank of arrays to be selected for a first operation, while a second bank of arrays is simultaneously selected for a second operation.
According to a third aspect of the present invention, a method of performing simultaneous operations within a concurrent flash memory circuit is provided. The method includes the steps of: providing first and second memory cell arrays, each having a first size; providing third and fourth memory cell arrays, each having a second size different from the first size; selecting a first bank of arrays including at least one of the first, second, third and fourth memory cell arrays; selecting a second bank of arrays the including the remaining of the first, second, third and fourth memory cell arrays; and performing a first operation on the first bank of arrays, while simultaneously performing a second operation on the second bank of arrays.